Development of digital application specific printed electronics circuits : from specification to final prototypes
Llamas, Manuel (Universitat Autònoma de Barcelona. Centre d'Accessibilitat i Intel·ligència Ambiental de Catalunya)
Mashayekhi, Mohammad (Universitat Autònoma de Barcelona. Centre d'Accessibilitat i Intel·ligència Ambiental de Catalunya)
Alcalde, Ana (Universitat Autònoma de Barcelona. Centre d'Accessibilitat i Intel·ligència Ambiental de Catalunya)
Carrabina Bordoll, Jordi (Universitat Autònoma de Barcelona. Departament de Microelectrònica i Sistemes Electrònics)
Pallarès, Jofre (Universitat Autònoma de Barcelona. Departament de Microelectrònica i Sistemes Electrònics)
Vila, Francesc (Universitat Autònoma de Barcelona. Departament de Microelectrònica i Sistemes Electrònics)
Conde Giménez, Adrià (Universitat Autònoma de Barcelona. Departament de Microelectrònica i Sistemes Electrònics)
Terés Terés, Lluís (Universitat Autònoma de Barcelona. Departament de Microelectrònica i Sistemes Electrònics)

Fecha:	2015
Resumen:	This paper presents a global proposal and methodology for developing digital printed electronics (PE) prototypes, circuits and application specific printed electronics circuits (ASPECs). We start from a circuit specification using standard Hardware Description Languages (HDL) and executing its functional simulation. Then we perform logic synthesis that includes logic gate minimization by applying state-of-the-art algorithms embedded in our proposed electronic design automation (EDA) tools to minimize the number of transistors required to implement the circuit. Later technology mapping is applied, taking into account the available technology, (i. e. , PMOS only technologies) and the cell design style (either Standard Cells or Inkjet Gate Array). These layout strategies are equivalent to those available in application specific integrated circuits (ASICs) flows but adapting them to Printed Electronics, which vary greatly depending on the targeted technology. Then Place & Route tools perform floorplan, placement and wiring of cells, which will be checked by the corresponding layout versus schematic (LVS). Afterwards we execute an electrical simulation including parasitic capacitances and relevant parameters. Finally, we obtain the prototypes which will be characterized and tested. The most important aspect of the proposed methodology is that it is portable to different PE processes, so that considerations and variations between different fabrication processes do not affect the validity of our approach. As final results, we present fabricated prototypes that are currently being characterized and tested.
Ayudas:	European Commission 287682 Ministerio de Economía y Competitividad TEC2011-29800-C03
Derechos:	Tots els drets reservats.
Lengua:	Anglès
Documento:	Article ; recerca ; Versió acceptada per publicar
Materia:	Digital circuits ; Electronic design automation ; Hardware description languages ; Printed circuit layout ; Prototypes
Publicado en:	Journal of Display Technology, Vol. 11, No. 8 (August 2015) , p. 652-657, ISSN 1551-319X

DOI: 10.1109/JDT.2015.2404974

Post-print 6 p, 794.2 KB

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