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Página principal > Libros y colecciones > Capítulos de libros > Simulating the impact of random telegraph noise on integrated circuits |
Publicación: | VDE Verlag GmbH, 2021 |
Descripción: | 4 pàg. |
Resumen: | This paper addresses the statistical simulation of integrated circuits affected by Random Telegraph Noise (RTN). For that, the statistical distributions of the parameters of a defect-centric model for RTN are experimentally determined from a purposely designed integrated circuit with CMOS transistor arrays. Then, these distribution functions are used in a statistical simulation methodology that, taking into account transistor sizes, biasing conditions and time, can assess the impact of RTN in the performance of an integrated circuit. Simulation results of a simple circuit are shown together with experimental measurements of a circuit with the same characteristics implemented in the same CMOS technology. |
Ayudas: | Agencia Estatal de Investigación PID2019-103869RB Ministerio de Ciencia e Innovación BES-2017-080160 |
Nota: | La conferència també és coneguda com a SMACD/PRIME 2021 - International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design and 16th Conference on PhD Research in Microelectronics and Electronics |
Derechos: | Tots els drets reservats. |
Lengua: | Anglès |
Documento: | Capítol de llibre ; recerca ; Versió acceptada per publicar |
Materia: | Characterization ; CMOS ; RTN ; Simulation ; Transistor |
Publicado en: | SSMACD / PRIME 2021: International Conference on SMACD and 16th Conference on PRIME, 2021, p. 1-4, ISBN 978-3-8007-5588-2 |
Postprint 5 p, 2.0 MB |